ACK! dAck! 2.0 Manuel d'utilisateur télécharger pdf (Page 12)

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation Rev. 02 — 23 October 2000 12 of 73

9397 750 07648

DMA registers

DMA Command DMA controller 30 controls all DMA transfers 1

DMA Transfer Counter DMA controller 34 sets byte count for DMA Transfer 4

DMA Conﬁguration DMA controller 38 (byte 0) sets GDMA conﬁguration (counter enable,

burst length, data strobing, bus width)

39 (byte 1) sets ATA conﬁguration (IORDY enable,

mode selection: ATA/UDMA/MDMA/PIO)

DMA Hardware DMA controller 3C endian type, master/slave selection, signal

polarity for DACK, DREQ, DIOW, DIOR

1F0 Task File ATAPI peripheral 40 single address word register: byte 0 (lower

byte) is accessed ﬁrst

1F1Task File ATAPI peripheral 48 IDE device access 1

1F2 Task File ATAPI peripheral 49 IDE device access 1

1F3 Task File ATAPI peripheral 4A IDE device access 1

1F4 Task File ATAPI peripheral 4B IDE device access 1

1F5 Task File ATAPI peripheral 4C IDE device access 1

1F6 Task File ATAPI peripheral 4D IDE device access 1

1F7 Task File ATAPI peripheral 44 IDE device access (write only; reading

returns 00H)

3F6 Task File ATAPI peripheral 4E IDE device access 1

3F7 Task File ATAPI peripheral 4F IDE device access 1

DMA Interrupt Reason DMA controller 50 (byte 0) shows reason (source) for DMA interrupt 1

51 (byte 1) 1

DMA Interrupt Enable DMA controller 54 (byte 0) enables DMA interrupt sources 1

55 (byte 1) 1

DMA Endpoint DMA controller 58 selects endpoint FIFO, data ﬂow direction 1

DMA Strobe Timing DMA controller 60 strobe duration in UDMA/MDMA mode 1

General registers

Interrupt device 18 shows interrupt sources 4

Chip ID device 70 product ID code and hardware version 3

Frame Number device 74 last successfully received Start Of Frame:

lower byte (byte 0) is accessed ﬁrst

Scratch device 78 allows save/restore of ﬁrmware status

during ‘suspend’

Unlock Device device 7C re-enables register access after ‘suspend’ 2

Test Mode PHY 84 direct setting of D+, D− states, loopback

mode, internal transceiver test (PHY)

Table 4: Register summary

…continued

Name Destination Address

(Hex)

Description Size

(bytes)

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 72 73

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ACK! dAck! 2.0 Manuel d'utilisateur Page 12

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