ACK! dAck! 2.0 Manuel d'utilisateur Page 11

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Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification Rev. 02 — 23 October 2000 11 of 73
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
8. Modes of operation
The ISP1581 has two bus configuration modes, selected via pin BUS_CONF/DA0 at
power-up:
Split Bus mode (BUS_CONF = 0): 8-bit multiplexed address/data bus and
separate 8-bit/16-bit DMA bus
Generic Processor mode (BUS_CONF = 1); separate 8-bit address and 16-bit
data bus
Details of the bus configurations for each mode are given in Table 3 . Typical interface
circuits for each mode are given in Section 13 “Application information”.
9. Register descriptions
Table 3: Bus configuration modes
BUS_CONF PIO width DMA width Description
DMAWD = 0 DMAWD = 1
0 AD[7:0] D[7:0] D[15:0] Split Bus mode: multiplexed address/data on pins AD[7:0];
separate 8/16-bit DMA bus on pins DATA[15:0]
1 A[7:0]
D[15:0]
D[7:0] D[15:0] Generic Processor mode: separate 8-bit address on pins
AD[7:0]; 16-bit data (PIO and DMA) on pins DATA[15:0]
Table 4: Register summary
Name Destination Address
(Hex)
Description Size
(bytes)
Initialization registers
Address device 00 USB device address + enable 1
Mode device 0C power-down options, global interrupt
enable, SoftConnect
1
Interrupt Configuration device 10 interrupt sources, trigger mode, output
polarity
1
Interrupt Enable device 14 interrupt source enabling 4
DMA Configuration DMA controller 38 see DMA registers 2
DMA Hardware DMA controller 3C see DMA registers 1
Data flow registers
Endpoint Index endpoints 2C endpoint selection, data flow direction 1
Control Function endpoint 28 endpoint buffer management 1
Data Port endpoint 20 data access to endpoint FIFO 2
Buffer Length endpoint 1C packet size counter 2
Endpoint MaxPacketSize endpoint 04 maximum packet size 2
Endpoint Type endpoint 08 selects endpoint type: control,
isochronous, bulk or interrupt
2
Short Packet endpoint 24 short packet received on OUT endpoint 2
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