ACK! dAck! 2.0 Manuel d'utilisateur Page 54

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Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification Rev. 02 — 23 October 2000 54 of 73
9397 750 07648
© Philips Electronics N.V. 2000. All rights reserved.
12.4 DMA timing
12.4.1 PIO mode
General
T
cy(RW)
read/write cycle time 60 - ns
t
AVLL
address set-up time before ALE LOW 3 - ns
t
I1VLL
R/W set-up time before ALE LOW 3 - ns
t
LLI2L
ALE LOW to DS LOW delay 5 - ns
t
I2HI1X
R/W hold time after DS HIGH 5 - ns
Table 83: Parallel I/O timing parameters: multiplexed address/data bus
…continued
Symbol Parameter Min Max Unit
(1) The device address consists of signals CS1, CS0, DA2, DA1 and DA0.
(2) The data bus width depends on the PIO access command used. Task File register access uses 8 bits (DATA[7:0]), except
for Task File register 1F0 which uses 16 bits (DATA[15:0]). DMA commands 04H and 05H also use a 16-bit data bus.
(3) The device can negate IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the
current cycle after t
su4
following the assertion of DIOR or DIOW. The following three cases are distinguished:
a) Device keeps IORDY released (high-impedance): no wait state is generated.
b) Device negates IORDY during t
su4
, but re-asserts IORDY before t
su4
expires: no wait state is generated.
c) Device negates IORDY during t
su4
and keeps IORDY negated for at least 5 ns after t
su4
expires: a wait state is
generated. The cycle is completed as soon as IORDY is re-asserted. For extended read cycles (DIOR asserted), the
read data on lines DATAn must be valid at t
d1
before IORDY is asserted.
(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.
Fig 13. PIO mode timing.
HIGH
(write) DATA
[
7:0
]
(2)
(read) DATA
[
7:0
]
(2)
device
(1)
address
valid
DIOR, DIOW
(4)
IORDY
(3a)
IORDY
(3b)
IORDY
(3c)
t
w1
t
w2
t
h1
t
su1
t
su2
t
su5
t
su4
t
su4
t
w3
t
h2
t
su3
t
d2
t
h3
(min)
T
cy1
MGT499
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