ACK! dAck! 2.0 Manuel d'utilisateur télécharger pdf (Page 45)

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation Rev. 02 — 23 October 2000 45 of 73

9397 750 07648

[1] Test circuit: see Figure 31.

[2] Excluding the ﬁrst transition from Idle state.

[3] Characterized only, not tested. Limits guaranteed by design.

Receiver timing

High-speed mode (Template 4,

Universal Serial Bus Speciﬁcation Rev. 2.0

)

- data source jitter and receiver

jitter tolerance

eye patterns of

Template 3 and

Template 4; see

Figure 9 and

Figure 10

[3]

see Tabl e 80

Full-speed mode

JR1

receiver data jitter tolerance to

next transition

see Figure 4

[3]

−18.5 - +18.5 ns

JR2

receiver data jitter tolerance for

paired transitions

see Figure 4

[3]

−9- +9ns

FEOPR

receiver SE0 width accepted as EOP;

see Figure 3

[3]

82--ns

FST

width of SE0 during differential

transition

rejected as EOP;

see Figure 5

[3]

--14ns

Table 76: Dynamic characteristics: analog I/O pins (D+, D−)

[1]

…continued

= 4.0 to 5.5 V; V

GND

=0V;T

amb

−

40 to

C; C

= 50 pF; R

= 1.5 k

Ω

on D

to V

TERM

.; unless otherwise speciﬁed.

Symbol Parameter Conditions Min. Typ Max Unit

PERIOD

is the bit duration corresponding with the USB data rate.

Full-speed timing symbols have a subscript preﬁx ‘F’, low-speed timings a preﬁx ‘L’.

Fig 3. Source differential data-to-EOP transition skew and EOP width.

MGR776

PERIOD

differential

data lines

crossover point

differential data to

SE0/EOP skew

N × T

PERIOD

+ t

DEOP

source EOP width: t

EOPT

receiver EOP width: t

EOPR

crossover point

extended

+3.3 V

0 V

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 72 73

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ACK! dAck! 2.0 Manuel d'utilisateur Page 45

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