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Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation Rev. 02 — 23 October 2000 6 of 73

9397 750 07648

MODE0/DA1 20 I/O during power-up: input to select the read/write strobe

functionality in generic processor mode

0 — Motorola style: pin 26 is R/

W and pin 27 is DS

1 — 8051 style: pin 26 is

RD and pin 27 is WR

normal operation: address output to select the task ﬁle

DA2 21 O address output to select the task ﬁle register of an ATAPI

device

READY/

IORDY

22 I/O Generic processor mode: ready signal (READY; output)

A LOW level signals that ISP1581 is processing a previous

command or data and is not ready for the next command or

data transfer; a HIGH level signals that ISP1581 is ready

for the next microprocessor read or write.

Split Bus mode: DMA ready signal (IORDY; input); used

for accessing ATAPI peripherals (PIO and UDMA modes

only).

AGND 23 - analog ground

CC(3.3)

24 - supply voltage (3.3 V ± 10%); supplies internal digital

circuits

CS 25 I chip select input

(R/

W)/RD 26 I input; function is determined by input MODE0 at power-up:

MODE0 = 0 — pin functions as R/

W (Motorola style)

MODE0 = 1 — pin functions as

RD (8051 style).

DS/WR 27 I input; function is determined by input MODE0 at power-up:

MODE0 = 0 — pin functions as

DS (Motorola style)

MODE0 = 1 — pin functions as

WR (8051 style).

INT 28 O interrupt output; programmable polarity (active HIGH or

LOW) and signaling (edge or level triggered)

ALE/A0 29 I input; function determined by input MODE1 during

power-up:

MODE1 = 0 — address latch enable; a falling edge latches

the address on the multiplexed address/data bus (AD[7:0])

MODE1 = 1 — address/data selection on AD[7:0]; a logic 1

indicates that an address will be written at the next

pulse; a logic 0 indicates that data will be written at the next

WR pulse; used in Split Bus mode only.

AD0 30 I/O bit 0 of multiplexed address/data

AD1 31 I/O bit 1 of multiplexed address/data

AD2 32 I/O bit 2 of multiplexed address/data

AD3 33 I/O bit 3 of multiplexed address/data

AD4 34 I/O bit 4 of multiplexed address/data

AD5 35 I/O bit 5 of multiplexed address/data

DGND 36 - digital ground

CC(5.0)

37 - supply voltage (3.3 or 5.0 V)

AD6 38 I/O bit 6 of multiplexed address/data

Table 2: Pin description for LQFP64

…continued

Symbol

[1]

Pin Type

[2]

Description

1 2 3 4 5 6 7 8 9 10 11 ... 72 73

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